Intel Ships Risk Wafers on 18A-P as Foundry Pivot Hinges on Performance Edge

Risk Production Begins Amid Foundry Repositioning

Intel has started risk production of 18A-P, an enhanced variant of its 18A process node that the company positions as a potential first commercial offering for external foundry customers. The milestone, disclosed at the IEEE VLSI Symposium in Hawaii last week, represents a shift in the foundry unit's go-to-market strategy under CEO Lip-Bu Tan, who has reportedly pushed to accelerate customer engagement on the 18A family rather than waiting for the more advanced 14A node originally planned as the flagship external offering.

Risk production refers to the initial low-volume manufacturing runs used to validate process readiness before full-scale commercial deployment. Intel says the start of 18A-P risk production keeps the company on the timeline it has communicated to prospective foundry partners, a critical signal in an industry where schedule predictability often matters as much as raw performance specifications.

The timing is significant. Intel launched its first 18A-based products in January with the Panther Lake Core Ultra Series 3 processors for client PCs. But the foundry business, which Tan has made central to Intel's turnaround narrative, has yet to announce a marquee external customer win on the node. Industry sources suggest that Apple is in discussions to manufacture certain silicon on either 18A or 18A-P, though no formal agreement has been disclosed.

Nine Percent Performance Lift, Full Design Compatibility

According to Intel, 18A-P delivers nine percent higher performance than baseline 18A at the same power envelope, or alternatively eighteen percent lower power consumption at the same performance level. The gains stem from what the company describes as co-optimization across transistor structures, interconnect layers, and design rule sets.

Crucially, Intel says 18A-P maintains full design rule compatibility with 18A. That means any chip layout targeting the original 18A specification can be ported to 18A-P without requiring a redesign of the physical implementation. For foundry customers evaluating Intel against TSMC or Samsung, this compatibility removes a layer of risk: a design can be started on 18A with confidence that it can take advantage of 18A-P improvements as soon as the enhanced process qualifies for volume production.

The compatibility claim is central to Intel's pitch. At DailyTechWire, we have tracked how foundry customers weigh not just peak process metrics but also the cost and schedule impact of mid-flight process changes. A design-rule-compatible enhancement allows a customer to lock in a tapeout schedule on 18A while preserving the option to capture 18A-P gains if timing aligns, effectively offering a free performance uplift without requalification overhead.

Industry observers now expect that some of Intel's first foundry customers may skip baseline 18A entirely and target 18A-P from the outset, particularly for products with launch windows in late 2027 or 2028 where 18A-P volume capacity will be available. This would let Intel showcase a more competitive power-performance profile in its first public foundry wins, a reputational advantage the company needs as it competes for design slots against incumbents.

A Third Variant for AI Accelerators

Intel is also developing 18A-PT, a variant optimized for through-silicon via integration. TSVs enable vertical stacking of dies or chiplets, a packaging architecture increasingly favored by designers of AI accelerators and high-bandwidth memory subsystems. By manufacturing logic and memory tiles separately and integrating them during advanced packaging, designers can optimize each tile on the most appropriate process node and achieve higher bandwidth and lower latency than traditional side-by-side chiplet layouts.

Intel expects 18A-PT to appeal specifically to AI hardware developers, where the ability to co-package custom logic with HBM stacks or SRAM cache chiplets is a differentiator. The company has not disclosed a risk production timeline for 18A-PT, but the roadmap suggests it will follow 18A-P by several quarters.

The three-variant strategy for 18A reflects a pragmatic response to the reality that no single process configuration can serve all workload requirements. By offering a baseline node, a performance-optimized variant, and a packaging-optimized variant, Intel is attempting to match the modularity that TSMC has long offered through its N-series portfolio and CoWoS advanced packaging options.

Long-Term Bets Beyond 18A

Intel also used the VLSI forum to preview technologies still in research phases. One is complementary FET, or CFET, which vertically stacks NMOS and PMOS transistors within the same footprint to increase transistor density without shrinking gate pitch further. CFET is widely seen as a successor to the gate-all-around nanosheet transistors that Intel and others have adopted at the 2nm-class nodes, though commercial deployment is likely several nodes away.

Another disclosed effort integrates gallium nitride power devices directly with silicon logic on the same die. GaN transistors can handle higher voltages and switch faster than silicon equivalents, making them attractive for power management in data center and edge AI systems. Integrating GaN with digital control logic in a monolithic process could reduce board complexity and improve power efficiency in server and accelerator designs, though Intel did not specify a timeline for productization.

These longer-term research disclosures serve a signaling function. For a foundry business trying to rebuild credibility after years of process delays, demonstrating a pipeline of innovation beyond the immediate node is part of the pitch to customers evaluating five-year roadmaps.

Execution Pressure and the Admission of Overreach

Intel's chief financial officer acknowledged earlier this month that the company had overextended itself during 18A development. Speaking at an industry conference, David Zinsner said the challenges around 18A last year stemmed from attempting too many simultaneous improvements and trying to optimize both performance and yield in parallel, a combination he likened to repairing an aircraft wing mid-flight.

The admission is notable. Intel has staked its foundry ambitions on proving it can execute a cadence of annual node transitions after years of delays on 10nm and subsequent nodes. Any perception of schedule risk on 18A or its variants could prompt customers to hedge by splitting designs across multiple foundries or defaulting to TSMC for critical products.

At DailyTechWire, we have followed how Intel's foundry strategy depends not just on delivering competitive process technology but on rebuilding the trust that comes from predictable execution. The decision to move forward with 18A-P risk production on schedule, despite the acknowledged challenges on baseline 18A, suggests the company is prioritizing timeline credibility as much as technical performance.

The other pressure point is capital intensity. Intel is simultaneously ramping three leading-edge nodes across multiple fabs in the United States and Ireland, while also investing in advanced packaging capacity and research on future nodes. The foundry business remains subscale compared to TSMC, meaning Intel must spread fixed costs across a smaller customer base. Winning external customers on 18A-P is therefore not just a revenue opportunity but a utilization imperative.

What the Risk Production Milestone Signals

Risk production is an intermediate gate, not a finish line. It indicates that the process is stable enough to produce test chips and early engineering samples, but volume readiness and customer qualification can take additional quarters. For Intel, the significance of starting 18A-P risk production lies in maintaining the narrative that the foundry unit is on track and that external customers can plan tape-outs with confidence.

The reported discussions with Apple, if they progress to a formal engagement, would be transformative for Intel Foundry. Apple's scale, technical rigor, and public visibility make it the most coveted foundry customer outside of hyperscalers building custom AI silicon. Even a modest allocation of Apple silicon to Intel's fabs would validate the foundry strategy in the eyes of other potential customers and investors.

But Apple is also known for rigorous process qualification and for maintaining dual-source or backup plans. Any engagement with Intel on 18A-P would likely start with a low-risk product, possibly an accessory chip or a secondary SKU, rather than a flagship application processor. That incremental approach would give Intel a reference customer without exposing Apple to single-source risk on a critical component.

For Intel, the path forward on 18A-P involves demonstrating yield ramp, securing at least one public design win, and showing that the enhanced process can compete on both performance and cost with TSMC's N3-series nodes, which are now in volume production. The company's ability to deliver on those milestones over the next twelve months will determine whether the foundry pivot can become a sustainable business or remains a strategic aspiration.