Packaging, Not Chips, Now Constrains AI Hardware Scale

The New Choke Point

In the race to deploy generative AI at scale, semiconductor manufacturers have spent the past three years pouring capital into leading-edge lithography and fab capacity. Yet a less visible constraint is now emerging: the physical infrastructure required to assemble, connect, and power those chips once they leave the cleanroom.

AT&S, an Austrian substrate supplier expanding its Malaysia operations, has flagged advanced packaging services and substrate production as the new bottleneck in AI hardware supply chains. According to CEO Michael Mertin, the complexity of modern AI accelerators has fundamentally reshaped vendor relationships, forcing chipmakers and packaging specialists into tighter coordination. "You have to cooperate, you have to think, you have to have a joint roadmap," Mertin noted during a recent visit to the company's Penang facility.

The observation underscores a structural shift in semiconductor economics. For two decades, the industry's chokepoints were concentrated upstream in wafer fabrication, where capital intensity, process control, and EUV tooling created natural barriers to entry. Today, as AI chips integrate high-bandwidth memory, chiplets, and heterogeneous dies, the engineering challenge has migrated downstream to packaging - a domain historically treated as low-margin assembly work.

Why Packaging Suddenly Matters

At DailyTechWire, we've tracked this transition closely across Taiwan, South Korea, and Southeast Asia. The pivot is driven by three converging forces.

First, AI accelerators now rely on advanced packaging techniques like chip-on-wafer-on-substrate (CoWoS), fan-out wafer-level packaging, and through-silicon vias to achieve the bandwidth and thermal performance required for large language models and multimodal inference. These processes demand specialized equipment, cleanroom-grade precision, and multi-month lead times - capabilities concentrated in a handful of suppliers.

Second, substrates themselves have become engineering artifacts. Modern AI chips require substrates with dozens of metal layers, micron-scale vias, and thermal dissipation pathways that can handle hundreds of watts. Producing these at volume requires investment cycles measured in years, not quarters, and the supply base remains narrow. AT&S, Ibiden, Unimicron, and a few others dominate the high-end market, and all are racing to add capacity.

Third, the interdependence between chip design, packaging architecture, and substrate specification has tightened. A chipmaker can no longer finalize a tape-out and simply hand it off to a packaging house. Thermal budgets, signal integrity, and mechanical stress must be co-optimized across the stack, forcing early and sustained collaboration between entities that once operated at arm's length.

Malaysia's Expanding Role

AT&S's decision to expand in Malaysia reflects broader industry dynamics. The country has quietly emerged as a critical node in the global packaging ecosystem, hosting operations from ASE, Unimicron, and now AT&S. Proximity to TSMC's advanced packaging lines in Taiwan, access to skilled labor, and government incentives have made Penang and Kulim attractive for substrate and back-end assembly.

The Austrian firm's investment signals confidence that AI demand will sustain substrate pricing and utilization rates well into the next cycle. Unlike commodity PCBs, high-layer-count substrates for AI accelerators carry gross margins above 30 percent, and lead times stretch six to nine months - a seller's market that has persisted even as memory and logic pricing softened in recent quarters.

Yet capacity additions take time. Substrate fabrication lines require clean environments, electroplating equipment, and laser drilling tools, and ramping yields on 20-plus layer designs is a multi-quarter process. AT&S and its peers are adding lines, but industry analysts estimate that substrate supply will remain tight through at least 2027, barring a sharp slowdown in AI capex.

Implications for the AI Stack

The packaging bottleneck introduces new risks for hyperscalers and AI startups alike. Lead times for custom silicon have stretched from twelve months to eighteen or more, with packaging and substrate procurement accounting for a growing share of the delay. Companies that locked in long-term supply agreements with TSMC, ASE, or Amkor early in the cycle enjoy an advantage; latecomers face allocation risk and premium pricing.

For chip designers, the shift elevates packaging from a back-end afterthought to a first-order design constraint. Startups building custom inference accelerators must now secure substrate and packaging commitments before finalizing die specs - a reversal of the traditional workflow. This front-loads capital requirements and lengthens time-to-market, favoring well-funded players with supply-chain expertise.

The dynamic also raises questions about geographic concentration. Advanced packaging capacity is heavily clustered in Taiwan, South Korea, and pockets of Southeast Asia. China has invested aggressively in packaging as a workaround to fab-level export controls, but high-end substrate production remains a gap. If geopolitical tensions disrupt cross-border flows of substrates or packaged dies, the AI hardware supply chain could face acute stress.

What Lies Ahead

Mertin's emphasis on joint roadmaps points to a future in which vertical integration and strategic partnerships become more common. We may see chipmakers acquire or invest in packaging specialists, or packaging houses move upstream into substrate production. TSMC's aggressive expansion of CoWoS capacity and Samsung's push into 2.5D and 3D packaging are early examples of this convergence.

At the same time, the substrate bottleneck creates an opening for new entrants and alternative materials. Startups exploring glass substrates, organic interposers, and novel dielectrics are attracting venture interest, though commercialization timelines remain long. Incumbents like AT&S will likely maintain their lead in the near term, but the technology landscape is in flux.

For now, the semiconductor industry faces a counterintuitive reality: building the chip is no longer the hardest part. Assembling, connecting, and powering it at scale is. As AI models grow and inference demand climbs, the companies that solve packaging and substrate constraints will capture as much value as those pushing Moore's Law forward.